From 046b947fb09a1fed471b5af716467bbc03f8783b Mon Sep 17 00:00:00 2001 From: Mark Langsdorf Date: Tue, 14 Jun 2011 12:46:29 +0100 Subject: [PATCH] x86/amd: Eliminate cache flushing when entering C3 on select AMD processors AMD Fam15h processors have a shared cache. It does not need=20 to be be flushed when entering C3 and doing so causes reduces performance. Modify acpi_processor_power_init_bm_check to prevent these processors from flushing when entering C3. Signed-off-by: Mark Langsdorf --- xen/arch/x86/acpi/cpu_idle.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index 23e8d3991e..9a416c7b2d 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -673,7 +673,8 @@ static void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flag flags->bm_check = 0; if ( num_online_cpus() == 1 ) flags->bm_check = 1; - else if ( c->x86_vendor == X86_VENDOR_INTEL ) + else if ( (c->x86_vendor == X86_VENDOR_INTEL) || + ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 0x15)) ) { /* * Today all MP CPUs that support C3 share cache. -- 2.30.2